EEPROM cells that support multiple programmed states are typically referred to as multi-level cells (MLC). As illustrated by FIG. 1, an MLC that supports an erased state and three different programmed states operates to store two data bits per cell. These and other aspects of an MLC having two data bits per cell is disclosed in an article by Takeuchi et al., entitled “A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 8, pp. 1228-1238, August (1998). Commonly assigned U.S. Pat. Nos. 5,862,074 and 5,768,188 also disclose aspects of multi-level EEPROM cells arranged in a NAND-type configuration, the disclosures of which are hereby incorporated herein by reference.
As further shown in FIG. 1, the different states supported by the MLC can be read using different threshold voltages as shown. For example, applying a threshold voltage between V1 and V2 will ideally activate the MLC if the cell is programmed to state 1. Furthermore, the other states can be discriminated from the first state using the different threshold voltages shown.
As shown in FIG. 2, one of the issues that can arise in using an MLC is that as the MLC is used to store more bits of information (such as a four bit MLC) the margin which may otherwise be present between the different states can be reduced so that less margin is available for the threshold voltage used to discriminate between the different states. Furthermore, several external factors (such as coupling and leakage, etc.) can further increase the distribution of the threshold voltages for the states. As shown in FIG. 2, the distribution of the threshold voltage that will activate cells in different states can overlap as shown by the highlighted regions. This overlap in threshold voltages for the different states can cause the MLC to generate errors when being read.